This invention discloses a technique to generate stretched solder columns (bumps) at the wafer level, suitable for wafer level packaging and having the following desirable characteristics: Low cost, excellent test and burn-in ability, and high thermal cycling reliability. More specifically, the invention describes (1) a technique of forming stretched solder columns on a functional wafer using a mechanical process (2) techniques to separate these stretched solder columns from a dummy wafer, leaving the stretched solder attached to only the functional wafer, and (3) the technique of forming the super stretched solder through controlled solidification.
Integrated Circuit (IC) devices, be they microprocessor or memory devices, will, in general, need to be connected to a printed circuit board (PCB). Besides providing electrical interconnection, microelectronic packaging also provides mechanical support and protection to the delicate IC and the interconnections, as well as providing thermal paths for heat dissipation. Microelectronic packaging, especially those used in commercial products, is also driven by lower cost and reduced size. Chip Scale Package (CSP) with small silicon-to-package area ratio is widely used in commercial portable products where size is of paramount importance.
Recently, there has been very high interest in Wafer Level Packaging (WLP). WLP, as the name implies, involves packaging at the wafer level and then mounting individual packages onto printed circuit boards (PCBs) using solder interconnections. WLP offers the lowest silicon-to-package area ratio possible. However, the main driver for WLP is the reduced cost associated with the integration of test and burn-in procedures at the wafer level, eliminating costly burn-in and test (BT) at the package level.
The main obstacle to implementing a WLBT process has been the problem of developing a full-wafer contact technology that has the process capability required for manufacturing [1]. In other words, the hundreds of test pins from the tester must be able to make contact with the corresponding solder bumps on the wafer. This requires a new approach to the design of test pins as well as very high co-planarity of the solder bumps.
Besides cost and testability, a good WLP design must also address an important issue in microelectronic assembly, namely thermal cycling reliability. A microelectronic assembly will experience millions of cycles of temperature excursion during field application due to power on-off. During each such temperature cycle, the silicon chip and the organic substrate/board expand and contract by different amounts due to different coefficients of thermal expansion. This thermal mismatch applies a high stress/strain to the solder that is interconnecting the silicon chip and the organic substrate/board, as illustrated in FIGS. 1a and 1b. FIG. 1a shows a schematic view of a chip 11 that has been attached to PCB 13 through solder bumps 12 while FIG. 1b shows 1a after it has been heated through arrows 14), as a result of which PCB 13 has expanded, relative to chip 11, by an amount d resulting in stress/strain on solder bumps 12. With the industry trend towards the use of larger dies (over 400 mm2) and miniaturized interconnections, the thermal cycling reliability of the interconnections has become more critical.
It is intuitive from FIG. 1b that the stress/strain on the interconnection can be reduced by increasing the length of standoff 12 and/or increasing the rotational freedom of the interconnection ends that are attached to the chip or the substrate.
A number of wafer level packaging schemes have been pursued by the industry to enhance the thermal cycling reliability of the solder interconnections. These include:
(1) Stacked Solder technique [2-4] where the standoff between the chip and the substrate is increased by multiple stacking of solder bumps/balls. However, this technique suffers from low process efficiency due to the sequential stacking processes.
(2) Copper Post technique [5-7] where the standoff between the chip and the substrate is increased through use of a copper column that is electroplated upwards from the under bump metalization (UBM) of the wafer. The main drawback of this process is the long electroplating duration as well as the expensive (material and capital) lithography process required to electroplate the copper column.
(3) Stress Buffer technique [8-10] where the UBM is formed on compliant polymeric layers that increase the rotational freedom of the solder interconnection. Besides the expensive lithography process, the improvement in thermal cycling reliability from enhanced rotational free is limited compared to that from an increasing standoff. All the above techniques also suffer from poor test and burn-in ability due to poor wafer level co-planarity of the solder bumps.